1. Field of the Invention
This invention relates to a sample and hold circuit device wherein input analog signals are sampled and held in a plurality of sample and hold circuits, and it also relates to a binary signal generating circuit and an A/D converter using said sample and hold circuit device.
2. Description of the Background Art
FIG. 4 is a block diagram showing the general arrangement of an A/D converter for converting analog signals into digital signals. In this figure, an analog signal inputted from an analog signal source AS to an analog signal input terminal 1 is fed to the individual comparators in a comparators group CMPG. These comparators have applied thereto corresponding reference voltages from a reference voltage generating circuit RV via reference voltage input terminals 2l-2n. Each comparator compares the input analog signal with the associated reference voltage and outputs a binary signal corresponding to the resulting value to output terminals Ol through On. These binary signals are fed to an encoder EC. The encoder EC encodes the binary signals fed thereto and outputs digital signals corresponding to the inputted analog signals.
As for the sample/hold function-equipped comparators group CMPG shown in FIG. 4, there is known a sample/hold function-equipped voltage comparators group in an A/D converter shown, for example, in "A CMOS 40 MHz 8b 105 mW Two-Step ACD" (N. Fukushima et al., ISSCC Digest of Tech. Papers, pp 14-15, Feb., 1989). FIG. 5 is a circuit diagram showing the sample/hold function-equipped voltage comparators group shown in the above-mentioned publication. In this figure, this sample/hold function-equipped comparators group is provided with a plurality of sample/hold function-equipped comparators (hereinafter referred to simply as the comparators) CMPj (j=1 .about.n, hereinafter the same). The input ends of the comparators CMPj are interconnected and are connected to an analog signal input terminal 1. Interposed between the internal nodes Nj of the comparators CMPj and said interconnected input ends are sampling switches SSj. The sampling switches SSj are used to determine the timing for sampling and holding in the comparators CMPj. Further, interposed between the internal nodes Nj and the reference voltage input terminals 2j are reference voltage applying switches SCj. The reference voltage input terminals 2j are fed with reference voltages REFj corresponding to the comparators from a reference voltage generating circuit RV, as described above. The reference voltage applying switches SCj are switches for introducing corresponding reference voltages to the comparators CMPj. The internal nodes Nj are connected together by a line L1 through averaging switches SAj. The averaging switches SAj are switches for uniforming variations in the voltages at the nodes Nj during sampling and holding. Coupling capacitors Cj are connected at one of their respective ends to the internal nodes Nj and at the other ends to the input ends of inverters IVj. The output ends of the inverters IVj are connected to output terminals Oj. Further, interposed between the respective input and output ends of the inverters IVj are input/output shorting switches SFj.
Referring to a timing chart shown in FIG. 6, the operation of the conventional device shown in FIG. 5 will now be described. In brief, the conventional device shown in FIG. 5 operates in three phases: a first phase P1, a second phase P2 and a third phase P3. In the first phase P1, an analog signal is introduced into the comparators CMPi to prepare for sampling and holding. In the second phase P2, effected are the sampling and holding of the analog signal and the averaging of the analog signal values sampled and held in the comparators CMPj. In the third phase P3, the analog signal is converted into a binary value on the basis of the reference voltage. A description of the operation in each phase will now be given in more detail.
First, in the first phase P1, the reference voltage applying switches SCj alone are turned off, while the other switches SSj, SAj and SFj are turned on. The turning-on of the input/output shorting switches SFj causes the input and output ends to be shorted, so that the potentials at the input and output ends are equal to each other (this operation is called "autozero"). At this time, the input and output voltages of the inverters IVj have a predetermined voltage value Vb (usually, about Vdd/2, where Vdd is the power source voltage) which is determined by the transmission characteristics of the inverters IVj and the condition that output voltage=input voltage. The other electrodes of the coupling capacitors Cj have applied thereto the voltage Vb. On the other hand, when the sampling switches SSj are turned on, one of the respective electrodes of the coupling capacitors Cj have applied thereto analog signal voltage Vin. As a result, the coupling capacitors Cj are charged in accordance with the difference between the voltages Vb and Vin.
As soon as the second phase P2 is started upon completion of the first phase P1, the sampling switches SSj are turned off, and the voltages Vaj of the analog signals inputted to the comparators CMPj at this point in time are sampled and held. The sampled and held analog signal voltages Vaj must be equal for all comparators CMPj. However, in practice, owing to skew in control signals inputted to the sampling switches SSj and differences in characteristics between the sampling switches SSj, the analog voltages sampled and held differ between the comparators. For example, in the case of a semiconductor integrated circuit device, it is impossible to arrange all of the n sampling switches SSj at an equal distance from the control signal generating source (not shown); skew is produced in the application timing for control signals. Even if these control signals are inputted to the sampling switches SSj with the same timing, a difference in the threshold voltages for the transistors used as the sampling switches would result in a difference between the respective timings for turning off the sampling switches SSj and hence the analog voltages to be sampled would differ between the comparators CMPj. The second phase P2 is provided also for the purpose of averaging such different sampled and held values to ensure that there is no contradiction in the outputs of all comparators CMPj. In this second phase P2, the averaging switches SAj still remain turned on. For this reason, even if the internal nodes Nj take different voltage values as a result of the comparators CMPj sampling and holding different analog signal voltage values, the internal nodes Ni.about.Nn of all comparators CMPj take the same voltage value Va through the line L1 to which the averaging switches SAj are connected. On the other hand, since the input/output shorting switches SFj still remain turned on in this phase, the coupling capacitors Cj are charged by the same potential difference, i.e., the potential difference between Va and Vb in the comparators CMPj.
In the third phase P3, the sampling switches SSj, the averaging switches SAj, and input/output shorting switches SFj are turned off, while the reference voltage applying switches SCj are turned on. The turning off of the reference voltage applying switches SFj results in the impedances of the input sides of the inverters IVj becoming infinite. Further, one of the respective electrodes of the coupling capacitors Cj have applied thereto a reference voltage Vrefj in place of the sampled and held value Va. Therefore, the voltage changes (Vrefj-Va) produced in one of the respective electrodes of the coupling capacitors Cj are transmitted to the output sides of the coupling capacitors Cj and inverted and amplified by the inverters IVj. That is, when the amplification factors of the inverters IVj are sufficiently large, the outputs of the comparators CMPj are: EQU Vdd, if Vj &gt;Vrefj and EQU Vss, if Vj &lt;Vrefj
where Vdd is the source voltage and Vss is the ground voltage. In the third phase P3, the voltage Va sampled and held in the second phase P2 is compared with the reference voltage Vefj in this manner, and binary signals (0 32 Vss, 1=Vdd) are outputted depending upon the result of comparison.
As described above, in the conventional sample/hold function-equipped comparators group used in A/C inverters, a sampling switch, an averaging switch and a reference voltage applying switch are provided for each comparator; thus, there has bee a problem that many switches are required, increasing the circuit area.